CHIPS Alliance
Open source IP, tools & standards for ASIC/FPGA
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Indexed project records; missing years are not zero. Coverage
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Links from the organization鈥檚 published listing (2024). Older contact links may have moved.
Programs & participation
3 records across 1 program2024Google Summer of CodeAnnual program 路 4 projects indexed
- Create a GDS reader/writer in OpenROAD
- GDS Reader/Writer in OpenROAD
- Relational Framework for Prompt-based Automatic Layout Generation with Glayout
- Support Zvk in T1 (RISC-V Vector coprocessor)
Source checked Sep 28, 2026
Participation imported from the GSoC Organizations archive snapshot; this historical listing is not an application-status claim.
2023Google Summer of CodeAnnual program 路 5 projects indexed
- 1st CLasS (Custom Logic as a Service) for Local FPGA Deployment using F4PGA
- DSP hard block integration in F4PGA
- Implement Zc RISC-V ISA Extension in Rocket Chip
- Implementation of a Common Python Framework for OpenFASoC Generators
- Makerchip Flows: A Suite of EDA Flow integrations for TL-Verilog ecosystem
Source checked Sep 28, 2026
Participation imported from the GSoC Organizations archive snapshot; this historical listing is not an application-status claim.
2022Google Summer of CodeAnnual program 路 3 projects indexed
- Development of a smart CI workflow to test analog block functionality and performance in OpenFASOC
- Improving the automatic layout generation of the mixed-signal temperature sensor block in OpenFASOC
- Verible SystemVerilog Preprocessor
Source checked Sep 28, 2026
Participation imported from the GSoC Organizations archive snapshot; this historical listing is not an application-status claim.